UPD16750中文资料瑞萨数据手册PDF规格书

FEATURES

· CMOS level input

· 384 outputs

· Input of 8 bits (gradation data) by 6 dots

· Capable of outputting 256 values by means of 8-by-2 external power modules (16 units) and a D/A converter

· Output dynamic range: VDD2 – 0.2 V to VSS2 + 0.2 V

· High-speed data transfer: fCLK = 40 MHz (internal data transfer speed when operating at 3.0 V)

· Apply for dot-line inversion, n-line inversion and column line inversion

· Output voltage polarity inversion function (POL)

· Display data inversion function (POL21/22)

· Logic power supply voltage (VDD1) : 3.3 V ± 0.3 V

· Driver power supply voltage (VDD2) : 9.0 V ± 0.5 V

· Low power control function (LPC)