UPD16724中文资料瑞萨数据手册PDF规格书

FEATURES

• CMOS level input

• 480 outputs

• Input of 8 bits (gray scale data) by 6 dots

• Capable of outputting 256 values by means of 9-by-2 external power modules (18 units) and a D/A converter

• Logic power supply voltage (VDD1): 2.3 to 3.6 V

• Driver power supply voltage (VDD2): 12.0 to 15.0 V (switchable: LPC)

• Output dynamic range: VSS2 + 0.2 V to VDD2 − 0.2 V

• High-speed data transfer: fCLK = 55 MHz MAX. (internal data transfer speed when operating at VDD1 = 3.0 V)

• Apply for 2 x 2 dot-line inversion

• Output voltage polarity inversion function (POL)

• Input data inversion function (POL21, POL22)

• Output reset control (MODE1)

• Slew rate control mode switching (MODE2)

• Slew rate control (SRC1, SRC2)

• Bias current control (LPC)