UPD16716中文资料瑞萨数据手册PDF规格书

FEATURES

• CMOS level input (2.5 to 3.6 V)

• 384 Outputs

• Input of 6 bits (gray scale data) by 6 dots

• Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter (RDAC)

• Logic power supply voltage (VDD1) : 2.5 to 3.6 V

• Driver power supply voltage (VDD2) : 15.0 V ± 0.5 V

• Output dynamic range VSS2 + 0.1 V to VDD2 – 0.1 V

• High-speed data transfer: fCLK = 70 MHz (internal data transfer speed when operating at VDD1 = 3.0 V), 45 MHz (internal data transfer speed when operating at VDD1 = 2.5 V)

• Apply for dot-line inversion, n-line inversion and column line inversion

• Output Voltage polarity inversion function (POL)

• Display data inversion function (capable of controlling by each input port) (POL21, POL22)

• Low power control function (LPC)