UPD16754中文资料瑞萨数据手册PDF规格书

FEATURES

• CMOS level input

• 384 Outputs

• Input of 8 bits (gradation data) by 6 dots

• Capable of outputting 256 values by means of 8-by-2 external power modules (16 units) and a D/A converter

• Logic power supply voltage (VDD1): 3.0 to 3.6 V

• Driver power supply voltage (VDD2): 8.5 to 9.5 V

• Output dynamic range VDD2 − 0.2 V to VSS2 + 0.2 V

• High-speed data transfer: fCLK = 40 MHz MAX. (internal data transfer speed when operating at VDD1 = 3.0 V)

• Apply for dot-line inversion, n-line inversion and column line inversion

• Output Voltage polarity inversion function (POL)

• Display data inversion function (POL21, POL22)