UPD16740中文资料瑞萨数据手册PDF规格书

FEATURES

· CMOS level input

· 384-output channel

· Input of 8 bits (gradation data) by 6 dots

· Capable of outputting 256 values by means of 11 external power modules and a D/A converter (C-DAC)

· Logic Part Power Supply Voltage (VDD1) : 3.3 ± 0.3 V

· Driver Part Power Supply Voltage (VDD2) : 8.5 ± 0.5 V

· High-speed data transfer: fMAX. = 40 MHz (internal data transfer speed when operating at VDD1 = 3.0 V)

· Output dynamic range VSS2 + 0.1 V to Vref – 0.1 V

· Apply for dot-line inversion, n-line inversion and column line inversion

· Output voltage polarity reverse is possible (POLA)

· Input data reverse function is incorporated (POLB)