TPS536C9中文资料具有 VR14 SVID 和 PMBus 的双通道十二相降压数字多相 D-CAP+™ 控制器数据手册TI规格书

描述 Description

The TPS536C9 is a VR14 SVID compliant step down controller with two channels, built-in non-volatile memory (NVM), and PMBus™ interface, and is fully compatible with TI NexFET™ power stages. Advanced control features such as the D-CAP+ architecture with undershoot reduction (USR) and overshoot reduction (OSR) provide fast transient response, low output capacitance, and good dynamic current sharing. The device also provides novel phase interleaving strategy and dynamic phase shedding for efficiency improvement at different loads. Adjustable control of output voltage slew rate and adaptive voltage positioning are natively supported. In addition, the device supports the PMBus communication interface for reporting the telemetry of voltage, current, power, temperature, and fault conditions to the host system. All programmable parameters can be configured through the PMBus interface and can be stored in NVM as the new default values, to minimize the external component count.

The TPS536C9 device is offered in a thermally enhanced 48-pin QFN packaged and is rated to operate from –40°C to 125°C.

特性 Features

• Input voltage range: 4.5 V to 17 V
• Dual output supporting N+M phase configurations (N+M ≤ 12, M ≤ 6)
• Backward compatible to VR13.HC/VR13.0 SVID
• Dynamic current limit for improved Fast-Vmode performance
• Enhanced D-CAP+ control to provider superior transient performance with excellent dynamic current sharing
• Configurable with non-volatile memory (NVM) for low external component count
• Individual per-phase IMON calibration, with multi-slope gain calibration to increase system accuracy.
• Diode braking with programmable timeout for reduced transient overshoot
• Programmable per-phase valley current limit (OCL)
• Programmable loop compensation through PMBus
• 6 mm × 6 mm, 48-pin, QFN package