TN2524数据手册Microchip中文资料规格书

描述 Description

This low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown.Vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired.

特性 Features

Low threshold (2.0V max.)
High input impedance
Low input capacitance (125pF max.)
Fast switching speeds
Low on-resistance
Free from secondary breakdown
Low input and output leakage