TMS320VC5503中文资料低功耗 C55x 定点 DSP- 高达 200MHz数据手册TI规格书

描述 Description

The TMS320VC5503 fixed-point digital signal processor (DSP) is based on the TMS320C55x DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal busstructure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity. The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit × 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU. The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions. The 64K bytes of on-chip memory on TMS320VC5503 is sufficient for many hand-held appliances, portable GPS systems, wireless speaker phones, portable PDAs, and gaming devices. Many of these appliances typically require 64K bytes or smaller amount of on-chip memory and need to operate in standby mode for morethan 60% to 70% of the time. For applications that require more than 64K bytes of on-chip memory but less than 128K bytes of memory, Texas Instruments (TI) offers the TMS320VC5507 device, which is based on the TMS320C55x DSP core. The general-purpose input and output functions and the 10-bit A/D provide sufficient pins for status, interrupts, and bit I/O for LCDs, keyboards, and media interfaces. The parallel interface operates in two modes, either as a slave to a microcontroller using the HPI port or as a parallel media interfaceusing the asynchronous EMIF. Serial media is supported through three McBSPs. The 5503 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM. Additional peripherals include real-time clock, watchdog timer, and I2C multi-master and slave interface. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The enhanced host-port interface (HPI) is a 16-bit parallel interface used to provide host processor access to 32K bytes of internal memory on the 5503. The HPI can be configured in either multiplexed or non-multiplexed mode to provide glueless interface to a wide variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention, providing DMA throughput of up to two 16-bit words per cycle. Two general-purpose timers, up to eight dedicated general-purpose I/O (GPIO) pins, and digital phase-locked loop (DPLL) clock generation are also included. The 5503 is supported by the industry's award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments' algorithm standard, and the industry's largest third-party network. The Code Composer Studio IDE features code generation tools including a C Compiler and Visual Linker, simulator, RTDX™, XDS510™ emulation device drivers, and evaluation modules. The 5503 is also supported by the C55x DSP Library whichfeatures more than 50 foundational software kernels (FIR filters, IIR filters,

特性 Features

• High-Performance, Low-Power, Fixed-Point TMS320C55™ Digital Signal Processor
• 108-, 144-, 200-MHz Clock Rate
• Dual Multipliers [Up to 400 Million Multiply-Accumulates per Second (MMACS)]
• Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
• 32K × 16-Bit On-Chip RAM, Composed of:
• 64K Bytes of One-Wait-State On-Chip ROM (32K × 16-Bit)
• 16-Bit External Parallel Bus Memory Supporting Either:
• Asynchronous Static RAM (SRAM)
• Synchronous DRAM (SDRAM)
• 16-Bit Parallel Enhanced Host-Port Interface (EHPI) With GPIO Capabilities
• Programmable Low-Power Control of Six Device Functional Domains
• On-Chip Peripherals
• Watchdog Timer
• Three Multichannel Buffered Serial Ports (McBSPs)
• Seven (LQFP) or Eight (BGA) General-Purpose I/O (GPIO) Pins and a General- Purpose Output Pin (XF)
• Real-Time Clock (RTC) With Crystal Input, Separate Clock Domain, Separate Power Supply
• IEEE Std 1149.1
• Packages:
• 179-Terminal MicroStar BGA™ (Ball Grid Array) (GHH and ZHH Suffixes)
• 1.35-V Core (144 MHz), 2.7-V - 3.6-V I/Os
• 1.6-V Core (200 MHz), 2.7-V - 3.6-V I/Os
C55x, eXpressDSP, Code Composer Studio, DSP/BIOS, RTDX, and XDS510 are trademarks of Texas Instruments. TMS320C55x and MicroStar BGA are trademarks of Texas Instruments.