TMS320VC5501数据手册集成电路（IC）的DSP（数字信号处理器）规格书PDF

描述 Description

The TMS320VC5501 (5501) fixed-point digital signal processor (DSP) is basedon the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two datawrite buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two datawrites in a single cycle. In parallel, the DMA controller can perform datatransfers independent of the CPU activity.

The C55x™ CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit × 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of theALUs is under instruction set control, providing the ability to optimizeparallel activity and power consumption. These resources are managed in theAddress Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x DSP generation supports a variable byte width instruction set forimproved code density. The Instruction Unit (IU) performs 32-bit program fetchesfrom internal or external memory and queues instructions for the Program Unit(PU). The Program Unit decodes the instructions, directs tasks to AU and DUresources, and manages the fully protected pipeline. Predictive branchingcapability avoids pipeline flushes on execution of conditional instructions.

The 5501 peripheral set includes an external memory interface (EMIF) thatprovides glueless access to asynchronous memories like EPROM and SRAM, as wellas to high-speed, high-density memories such as synchronous DRAM and synchronousburst RAM. Additional peripherals include UART, watchdog timer, and an I-Cache.Two full-duplex multichannel buffered serial ports (McBSPs) provide gluelessinterface to a variety of industry-standard serial devices, and multichannelcommunication with up to 128 separately enabled channels. The host-portinterface (HPI) is an 8-bit parallel interface used to provide host processoraccess to 16K words of internal memory on the 5501. The HPI operates inmultiplexed mode to provide glueless interface to a wide variety of hostprocessors. The DMA controller provides data movement for six independentchannel contexts without CPU intervention. Two general-purpose timers, eightdedicated general-purpose I/O (GPIO) pins, and analog phase-locked loop (APLL)clock generation are also included.

The 5501 is supported by the industry's award-winning eXpressDSP™, CodeComposer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments' algorithm standard, and the industry's largest third-party network. The Code Composer Studio× IDE features code generation tools that include a C Compiler, Visual Linker, simulator, RTDX™, XDS510™ emulation device drivers, and evaluation modules. The 5501 is also supported by the C55x™ DSP Library, which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip and board support libraries.

特性 Features

• High-Performance, Low-Power, Fixed-Point TMS320C55x™ Digital Signal Processor (DSP)
• 3.33-ns Instruction Cycle Time for 300-MHz Clock Rate
• 16K-Byte Instruction Cache (I-Cache)
• One/Two Instructions Executed per Cycle
• Dual Multipliers [Up to 600 Million Multiply-Accumulates Per Second (MMACS)]
• Two Arithmetic/Logic Units (ALUs)
• One Program Bus, Three Internal Data/Operand Read Buses, and Two Internal Data/Operand Write Buses

• Instruction Cache (16K Bytes)
• 16K × 16-Bit On-Chip RAM That is Composed of Four Blocks of 4K × 16-Bit Dual-Access RAM (DARAM) (32K Bytes)
• 16K × 16-Bit One-Wait-State On-Chip ROM (32K Bytes)
• 8M × 16-Bit Maximum Addressable External Memory Space
• 32-Bit External Parallel Bus Memory Supporting External Memory Interface (EMIF) With General-Purpose Input/Output (GPIO) Capabilities and Glueless Interface to:
• Asynchronous Static RAM (SRAM)
• Asynchronous EPROM
• Synchronous DRAM (SDRAM)
• Synchronous Burst RAM (SBRAM)

• Emulation/Debug Trace Capability Saves Last 16 Program Counter (PC) Discontinuities and Last 32 PC Values
• Programmable Low-Power Control of Six Device Functional Domains
• On-Chip Peripherals
• Six-Channel Direct Memory Access (DMA) Controller
• Two Multichannel Buffered Serial Ports (McBSPs)
• Programmable Analog Phase-Locked Loop (APLL) Clock Generator
• General-Purpose I/O (GPIO) Pins and a Dedicated Output Pin (XF)
• 8-Bit Parallel Host-Port Interface (HPI)
• Four Timers
• Two 64-Bit General-Purpose Timers
• 64-Bit Programmable Watchdog Timer
• 64-Bit DSP/BIOS™ Counter

• Inter-Integrated Circuit (I2C) Interface
• Universal Asynchronous Receiver/ Transmitter (UART)

• On-Chip Scan-Based Emulation Logic
• IEEE Std 1149.1
(JTAG) Boundary Scan Logic
• Packages:
• 176-Terminal LQFP (Low-Profile Quad Flatpack) (PGF Suffix)
• 201-Terminal MicroStar BGA™ (Ball Grid Array) (GZZ and ZZZ Suffixes)

• 3.3-V I/O Supply Voltage
• 1.26-V Core Supply Voltage
TMS320C55x, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments. C55x, eXpressDSP, Code Composer Studio, RTDX, and XDS510 are trademarks of Texas Instruments.