TMS320DM365中文资料DaVinci 数字媒体处理器数据手册TI规格书

描述 Description

Developers can now deliver pixel-perfect images at up to 720p H.264 at 30fps in their digital video designs without concerns of video format support, constrained network bandwidth, limited system storage capacity or cost with the new TMS320DM365 digital media processor based on DaVinci technology from Texas Instruments Incorporated (TI). With multi-format HD video, the DM365 also features a suite of peripherals saving developers on system costs.
This ARM9-based DM365 device offers speeds up to 300 MHz and supports production-qualified H.264, MPEG-4, MPEG-2, MJPEG and VC1/WMV9 codecs providing customers with the flexibility to select the right video codec for their application. These codecs are driven from video accelerators offloading compression needs from the ARM core so that developers can utilize the most performance from the ARM for their application. Video surveillance designers achieve greater compression efficiency providing more storage without straining the network bandwidth. Developers of media playback and camera-driven applications, such as video doorbells, digital signage, digital video recorders, portable media players and more can ensure interoperability as well as product scalability by taking advantage of the full suite of codecs supported on the DM365.
Along with multi-format HD video, the DM365 enables seamless interface to most additional external devices required for video applications. The image sensor interface is flexible enough to support CCD, CMOS, and various other interfaces such as BT.656, BT1120. The DM365 also offers a high level of integration with HD display support including, 3 built-in 10-bit HD Analog Video Digital to Analog Converters (DACs), DDR2/mDDR, Ethernet MAC, USB 2.0, integrated audio, Host Port Interface (HPI), Analog to Digital Converter, and many more features saving developers on overall system costs as well as real estate on their circuit boards allowing for a slimmer, sleeker design.

特性 Features

• Highlights
• Up to 300-MHz ARM926EJ-S Clock Rate
• Supports a Range of Encode, Decode, and Video Quality Operations
• HW Face Detect Engine
• 16-Bit Parallel AFE (Analog Front-End) Interface Up to 120 MHz
• 8-/16-bit YCC and Up to 24-Bit RGB888 Digital Output
• Hardware On-Screen Display (OSD)
• Capable of 720p 30fps H.264 video processingNote: 216-MHz is only capable of D1 processing
• 8 Different Boot Modes and Configurable Power-Saving Modes
• Extended temperature (-40°C - 85°C) available for 300-Mhz device
• 338-Pin Ball Grid Array at 65nm Process Technology
• High-Performance Digital Media System-on-Chip (DMSoC)
• Fully Software-Compatible With ARM9™
• ARM926EJ-S™ Core
• DSP Instruction Extensions and Single Cycle MAC
• EmbeddedICE-RT Logic for Real-Time Debug
• ARM9 Memory Architecture
• 8K-Byte Data Cache
• 16K-Byte ROM
• Two Video Image Co-processors (HDVICP, MJCP) Engines
• H.264, MPEG4, MPEG2, MJPEG, JPEG, WMV9/VC1
• Video Processing Subsystem
• HW Face Detect Engine
• Resize Engine
• Separate Horizontal/Vertical Control
• IPIPE Interface (IPIPEIF)
• 16-Bit Parallel AFE (Analog Front End) Interface Up to 120 MHz
• BT.601/BT.656/BT.1120 Digital YCbCr 4:2:2 (8-/16-Bit Module
• Lens distortion correction module (LDC)
• Back End Provides:
• Composite NTSC/PAL video encoder output
• 3 DACs for HD Analog Video Output
• BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
• Analog-to-Digital Convertor (ADC)
• Real Time Clock
• 16-Bit Host-Port Interface (HPI)
• IEEE 802.3 Compliant
• Management Data I/O (MDIO) Module
• Key Scan
• External Memory Interfaces (EMIFs)
• Asynchronous16-/8-bit Wide EMIF (AEMIF)
• NAND (8-/16-bit Wide Data)
• OneNAND(16-bit Wide Data)
• Flash Card Interfaces
• SmartMedia/xD
• Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
• USB 2.0 High-Speed Device
• USB On The Go (HS-USB OTG)
• Four 64-Bit General-Purpose Timers (each configurable as two 32-bit timers)
• Two UARTs (One fast UART with RTS and CTS Flow Control)
• One Master/Slave Inter-Integrated Circuit (I2C) Bus™
• I2S
• S/PDIF via Software
• SPI Protocol (Master Mode Only)
• Time Division Multiplexed Mode (TDM)
• Four Pulse Width Modulator (PWM) Outputs
• Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
• On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, UART, USB, SPI, EMAC, or HPI
• Configurable Power-Saving Modes
• Flexible PLL Clock Generators
• IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
• Device Revision ID Readable by ARM
• 338-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0.65-mm Ball Pitch
• 3.3-V and 1.8-V I/O, 1.2-V/ 1.35-V Internal
• TI E2E Community
• TI Embedded Processors Wiki

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