TMS320DM335中文资料数字媒体片上系统 (DMSoC)数据手册TI规格书

描述 Description

The DM335 processor is a low-cost, low-power processor providing advanced graphical user interface for display applications that do not require video compression and decompression. Coupled with a video processing subsystem (VPSS) that provides 720p display, the DM335 processor is powered by a 135/216-MHz ARM926EJ-S core so developers can create feature-rich graphical user interfaces allowing customers to interact with their portable, electronic devices such as video-enabled universal remote controls, Internet radio, e-books, video doorbells, and digital telescopes. The new DM335 is packed with the same peripherals as its predecessor, the TMS320DM355 device, including high-speed USB 2.0 on-the-go, external memory interface (EMIF), mobile DDR/DDR2, two SDIO ports, three UART Ports, two Audio Serial Ports, three SPI Ports, and SLC/MCL NAND Flash memory support. These peripherals help customers create DM335 processor-based designs that add video and audio excitement to a wide range of today's static user-interface applications while keeping silicon costs and power consumption low. The new digital media processor is completely scalable with the DM355 processor and Digital Video Evaluation Board (DVEVM), allowing customers to utilize their same code for their new DM335 processor focused designs.
The new DM335 device delivers a sophisticated suite of capabilities allowing for flexible image capture and display. Through its user interface technology, such as a four-level on-screen display, developers are able to create picture-within-picture and video-within-video as well as innovative graphic user interfaces. This is especially important for portable products that require the use of button or touch screen, such as portable karaoke, video surveillance and electronic gaming applications. Additional advanced capture and imaging technologies include support for CCD/CMOS image sensors, resize capability and video stabilization. The 1280-by-960-pixel digital LCD connection runs on a 75-MHz pixel clock and supports TV composite output for increased expandability. This highly integrated device is packaged in a 13 x 13 mm, 337 pin , 0.65 mm pitch BGA package.
The DM335 processor core is an ARM926EJ-S RISC processor. The ARM926EJ-S is a 32-bit processor core that performs 32-bit and 16-bit instructions and processes 32-bit, 16-bit, and 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core incorporates:
A coprocessor 15 (CP15) and protection moduleData and program Memory Management Units (MMUs) with table look-aside buffers. Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).The DM335 device has a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals:
A Video Processing Front-End (VPFE) A Video Processing Back-End (VPBE) The VPFE port provides an interface for CCD/CMOS imager modules and video decoders. The VPBE provides hardware On Screen Display (OSD)support and composite NTSC/PAL and digital LCD output.
The DM335 peripheral set includes:
An inter-integrated circuit (I2C) Bus interface Two audio serial ports (ASP) Three 64-bit general-purpose timers each configurable as two independent 32-bit timers A 64-bit watchdog timer Up to 104-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals Three UARTs with hardware handshaking support on one UART Three serial port Interfaces (SPI) Four pulse width modulator (PWM) peripherals Four real time out (RTO) outputs Two Multi-Media Card / Secure Digital (MMC/SD/SDIO) interfaces Wireless interfaces (Bluetooth, WLAN, WUSB) through SDIO A USB 2.0 full and high-speed device and host interface Two external memory interfaces:An asynchronous external memory interface (AEMIF) for slower memories/peripherals such as NAND and OneNAND, A high speed synchronous memory interface for DDR2/mDDR. For software development support the DM335 has a complete set of ARM development tools which include: C compilers, assembly optimizers to simplify programming and scheduling, and a Windows™debugger interface for visibility into source code execution.

特性 Features

• Highlights
• Up to 216-MHz ARM926EJ-STM Clock Rate
• Video Processing Subsystem
• Up to 14-bit CCD/CMOS Digital Interface
• Resize Image 1/16x to 8x
• Up to 75-MHz Pixel Clock
• Peripherals include DDR and mDDR SDRAM, 2 MMC/SD/SDIO and SmartMedia Flash Card Interfaces, USB 2.0, 3 UARTs and 3 SPIs
• Configurable Power-Saving Modes
• 3.3-V and 1.8-V I/O, 1.3-V Core
• Up to 104 General-Purpose I/O (GPIO) Pins
• High-Performance Digital Media System-on-Chip
• Fully Software-Compatible With ARM™
• ARM926EJ-S Core
• DSP Instruction Extensions and Single Cycle MAC
• EmbeddedICE-RT™ Logic for Real-Time Debug
• ARM9 Memory Architecture
• 8K-Byte Data Cache
• 8K-Byte ROM
• Video Processing Subsystem
• Hardware IPIPE for Real-Time Image Processing
• 16-/8-bit Generic YcBcR-4:2 Interface (BT.601)
• Up to 75-MHz Pixel Clock
• Resize Engine
• Separate Horizontal/Vertical Control
• Back End Provides:
• Composite NTSC/PAL video encoder output
• BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
• External Memory Interfaces (EMIFs)
• Asynchronous16-/8-bit Wide EMIF (AEMIF)
• NAND (8-/16-bit Wide Data)
• Flash Card Interfaces
• SmartMedia
• Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
• USB 2.0 Full and High-Speed Device
• Three 64-Bit General-Purpose Timers (each configurable as two 32-bit timers)
• Three UARTs (One fast UART with RTS and CTS Flow Control)
• One Master/Slave Inter-Integrated Circuit (I2C) Bus®
• I2S and TDM I2S
• S/PDIF via Software
• SPI Protocol (Master Mode Only)
• Four Pulse Width Modulator (PWM) Outputs
• Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
• Configurable Power-Saving Modes
• Flexible PLL Clock Generators
• IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
• Device Revision ID Readable by ARM
• 337-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0.65-mm Ball Pitch
• 3.3-V and 1.8-V I/O, 1.3-V Internal
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• TI Embedded Processors Wiki

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