TMS320C6670中文资料用于通信和电信的 4 核定点和浮点 DSP数据手册TI规格书

描述 Description

The TMS320C6670 Multicore Fixed and Floating Point System on Chip is a member of the C66xx SoC family based on TI's new KeyStone Multicore SoC Architecture designed specifically for high performance applications such as software defined radio, emerging broadband and other communications segments. Integrated with four C66x CorePac DSPs, each core runs at 1.0 to 1.20 GHz enabling up to 4.8 GHz. Hardware acceleration provides a highly integrated, power efficient and easy to use platform for implementing a combination of multi-band, multi-standard waveforms, including proprietary air-interfaces. The C6670 platform is power efficient and easy to use. The C66x CorePac DSP is fully backward compatible with all existing C6000 family of fixed and floating point DSPs.

特性 Features

• Four TMS320C66x DSP Core Subsystems at 1.00 GHz and 1.2GHz
• 153.6 GMAC/76.8 GFLOP @ 1.2GHz
• 32KB L1P, 32KB L1D, 1024KB L2 Per Core
• 2MB Shared L2

• Multicore Navigator and TeraNet Switch Fabric - 2 Tb
• Network Coprocessors- Packet Accelerator, Security Accelerator
• Four Lanes of SRIO 2.1 - 5 Gbaud Per Lane Full Duplex
• Two Lanes PCIe Gen2 - 5 Gbaud Per Lane Full Duplex
• HyperLink - 50Gbaud Operation, Full Duplex
• Ethernet MAC Subsystem - Two SGMII Ports w/ 10/100/1000 Mbps operation
• 64-Bit DDR3 Interface (DDR3-1600) - 8 GByte Addressable Memory Space
• Six Lane SerDes-Based Antenna Interface (AIF2) - Operating at up to 6.144 Gbps
• Hardware Coprocessors
• -Enhanced Coprocessor for Turbo Encoding -Three Enhanced Coprocessors for Turbo Decoding -Four Viterbi Decoders -Three Fast Fourier Transform Coprocessors -Bit Rate CoProcessor -Two Receiver Accelerators for WCDMA -Transmitt Accelerator for WCDMA

• Four Rake Search Accelerators for Chip Rate Processing and Reed-Muller Decoding
• I2C Interface, 16 GPIO Pins, SPI Interface
• Eight 64-Bit Timers, Three On-Chip PLLs