TJ2997中文资料DDR Termination Regulator数据手册HTC Korea规格书

描述 Description

The TJ2997 linear regulator is designed to meet the JEDEC SSTL specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering up to 1.5A continuous current and transient peaks up to 3A with respect to PVIN operating condition in the application as required for DDR-SDRAM termination. The TJ2997 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs. An additional feature found on the TJ2997 is an active high enable (EN) pin that provides Suspend To RAM (STR) functionality. When EN is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.

特性 Features

- Source and sink current
- Low output voltage offset
- No external resistors required
- Linear topology
- Suspend to Ram (STR) functionality
- Low external component count
- Thermal Shutdown
- Available in SOP8, SOP8-PP Packages