TJ2995中文资料DDR Termination Regulator数据手册HTC Korea规格书

描述 Description

The TJ2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for terminationof DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to loadtransient. This device can deliver 1.5A continuous current and transient peaks up to 3A in the application asrequired for DDR-SDRAM termination. With an independent VSENSE pin, the TJ2995 can provide superior loadregulation. The TJ2995 provides a VREF output as the reference for the chipset and DDR DIMMS. The TJ2995can easily provide the accurate VTT and VREF voltages without external resistors that PCB areas can bereduced. The quiescent current is low to meet the low power consumption applications.

特性 Features

- Low Output Voltage Offset
- Works with +5V, +3.3V, and 2.5V Rails
- Source and Sink Current
- Low External Component Count
- No External Resistors Required
- Linear Topology
- Available in SOP8, SOP8-PP Package
- Low Cost and Easy to Use