TJ2996中文资料DDR Termination Regulator数据手册HTC Korea规格书

描述 Description

The TJ2996 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM.The device contains a high-speed operational amplifier to provide excellent response to loadtransient. The output stage prevents shoot through while delivering 1.5A continuous current and transientpeaks up to 3A in the application as required for DDR-SDRAM termination. The TJ2996 also incorporates aVSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.An additional feature found on the TJ2996 is an active low shutdown pin that provides Suspend To RAM(STR) functionality. When is pulled low the VTT output will tri-state providing a high impedance output,but, VREF will remain active. A power savings advantage can be obtained in this mode through lowerquiescent current.

特性 Features

- Source and sink current
- Low output voltage offset
- No external resistors required
- Linear topology
- Suspend to Ram (STR) functionality
- Low external component count
- Thermal Shutdown
- Available in SOP8, SOP8-PP Packages