DDR Termination Regulator

文件：973.1 Kbytes 页数：14 Pages

HTCHTC Korea TAEJIN Technology Co.，LTD

泰进韩国泰进技术股份有限公司

DDR Termination Regulator

The TJ2996 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM.The device contains a high-speed operational amplifier to provide excellent response to loadtransient. The output stage prevents shoot through while delivering 1.5A continuous curr - Source and sink current\n- Low output voltage offset\n- No external resistors required\n- Linear topology\n- Suspend to Ram (STR) functionality\n- Low external component count\n- Thermal Shutdown\n- Available in SOP8, SOP8-PP Packages;

HTC Korea

泰进

DDR Termination Regulator

文件：973.1 Kbytes 页数：14 Pages

HTCHTC Korea TAEJIN Technology Co.，LTD

泰进韩国泰进技术股份有限公司

DDR Termination Regulator

文件：973.1 Kbytes 页数：14 Pages

HTCHTC Korea TAEJIN Technology Co.，LTD

泰进韩国泰进技术股份有限公司