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描述 Description

The TDA4VE TDA4AL TDA4VL processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The TDA4AL provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.

Key Performance Cores Overview: The “C7x” next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating-point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. The new “MMA” deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated Vision hardware accelerators provide vision pre-processing with no impact on system performance.

General Compute Cores and Integration Overview: Separate dual core cluster configuration of Arm® Cortex®-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Up to four Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72 core’s unencumbered for applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D levels while the integrated security features protect data against modern day attacks. CSI2.0 ports enable multi sensor inputs. To further the integration, the TDA4VE TDA4AL TDA4VL family also includes an MCU island eliminating the need for an external system microcontroller.

特性 Features

Processor cores:
• Deep-learning matrix multiply accelerator (MMA), up to 8 TOPS (8b) at 1.0 GHz
• Depth and Motion Processing Accelerators (DMPAC)
• 1MB shared L2 cache per dual-core Cortex-A72 cluster
• Up to Six Arm Cortex-R5F MCUs at up to 1.0 GHz
• Two Arm Cortex-R5F MCUs in isolated MCU subsystem
• GPU IMG BXS-64-4, 256kB Cache, up to 800 MHz, 50 GFLOPS, 4 GTexels/s (TDA4VE and TDA4VL)
• Up to 4MB of on-chip L3 RAM with ECC and coherency
• Shared coherent cache
• Up to Two External Memory Interface (EMIF) modules with ECC
• Supports speeds up to 4266 MT/s
• General-Purpose Memory Controller (GPMC)
• Functional Safety-Compliant targeted (on select part numbers)
• Documentation available to aid ISO 26262 functional safety system design up to ASIL-D/SIL-3 targeted
• Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
• Hardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main Domain
• ISO 26262 planned
• Secure boot with secure runtime support
• Embedded hardware security module
• One PCI-Express (PCIe) Gen3 controllers
• Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
• One USB 3.0 dual-role device (DRD) subsystem
• Supports Type-C switching
• Two CSI2.0 4L RX plus Two CSI2.04L TX
• Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support
• One (TDA4AL/TDA4VL) or Two (TDA4VE) DSI 4L TX (up to 2.5K)
• One DPI
• Five Multichannel Audio Serial Port (MCASP) modules
• TDA4VE: H.264/H.265 Encode/Decode (up to 480 MP/s)
• TDA4VL: H.264/H.265 Encode/Decode (up to 240 MP/s)
• Two RMII/RGMII interfaces
• Embedded MultiMediaCard Interface ( eMMC™ 5.1)
• Two simultaneous flash interfaces configured as
• One QSPI
• 16-nm FinFET technology
• Functional Safety-Compliant support up to ASIL-D / SIL-3 targeted
• Flexible mapping to support different use cases