TDA4VH-Q1数据手册TI中文资料规格书

描述 Description

TDA4VH TDA4AH TDA4VP TDA4AP 处理器系列基于不断发展的 Jacinto™ 7 架构，面向 ADAS 和自动驾驶车辆 (AV) 应用，基于 TI 在 ADAS 处理器市场上十多年的先进地位所积累的广泛市场知识而构建。在以符合功能安全标准为目标的架构中，独特的高性能计算、深度学习引擎、信号和图像处理专用加速器的组合使 TDA4VH TDA4AH TDA4VP TDA4AP 器件非常适合多种成像、视觉、雷达、传感器融合和 AI 应用，例如：机器人、移动机械、非公路用车控制器、机器视觉、AI 盒、网关、零售自动化、医疗成像等。TDA4VH TDA4AH TDA4VP TDA4AP 以业界卓越的功耗/性能比为传统和深度学习算法提供高性能计算，并具有很高的系统集成度，可使支持集中式 ECU 或独立传感器中多种传感器模式的高级汽车平台实现可扩展性和更低的成本。关键内核包括具有标量和矢量内核的下一代 DSP、专用深度学习和传统算法加速器、用于通用计算的最新 Arm 和 GPU 处理器、集成式下一代成像子系统 (ISP)、视频编解码器、以太网集线器以及隔离式 MCU 岛。所有这些都由汽车级安全硬件加速器提供保护。

主要高性能内核概述

“C7x”下一代 DSP 将 TI 业界先进的 DSP 和 EVE 内核整合到单个性能更高的内核中，并增加了浮点矢量计算功能，从而实现了对旧代码的向后兼容性，同时简化了软件编程。在典型的汽车最高结温 125°C 下运行时，新型“MMA”深度学习加速器可在业界超低的功率范围内实现高达 8TOPS 的性能。专用的 ADAS/AV 硬件加速器可提供视觉预处理以及距离和运动处理，而不会影响系统性能。

通用计算内核和集成概述

对 Arm Cortex-A72 的独立八核集群配置有助于实现多操作系统应用，而且对软件管理程序的需求非常低。八个 Arm® Cortex®-R5F 子系统能够管理低级的时序关键型处理任务，使 Arm® Cortex®-A72 内核不受应用的影响。集成的 IMG BXS-4-64 GPU 可提供高达 50GFLOPS 的性能，从而为增强视觉应用实现动态 3D 渲染。TI 的第 7 代 ISP 以现有出色的 ISP 为基础，能够灵活地处理更广泛的传感器套件，支持更高的位深度，并且具有面向分析应用的特性。集成的诊断和安全功能可支持高达 ASIL-D/SIL-3 级别的操作，同时集成的安全功能可保护数据免受现代攻击。为了实现需要大量数据带宽的系统，提供了 PCIe 集线器和千兆位以太网交换机以及 CSI-2 端口，以支持众多传感器输入的吞吐量。为了进一步集成，TDA4VH TDA4AH TDA4VP TDA4AP 系列还包含一个 MCU 岛，无需使用外部系统微控制器。

特性 Features

Processor cores:
• Up to Four C7x floating point, vector DSP, up to 1.0 GHz, 320 GFLOPS, 1024 GOPS
• Up to Four Deep-learning matrix multiply accelerator (MMA), up to 32 TOPS (8b) at 1.0 GHz
• TwoVision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
• Depth and Motion Processing Accelerators (DMPAC)
• Eight Arm Cortex-A72 microprocessor subsystem at up to 2.0 GHz
• 2MB shared L2 cache per quad-core Cortex-A72 cluster
• 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core

• Eight Arm Cortex-R5F MCUs at up to 1.0 GHz
• 16K I-Cache, 16K D-Cache, 64K L2 TCM
• Two Arm Cortex-R5F MCUs in isolated MCU subsystem
• Six Arm Cortex-R5F MCUs in general compute partition

• GPU IMG BXS-64-4, 256kB Cache, up to 800 MHz, 50 GFLOPS, 4 GTexels/s
• Custom-designed interconnect fabric supporting near max processing entitlement Memory subsystem:
• Up to 8MB of on-chip L3 RAM with ECC and coherency
• ECC error protection
• Shared coherent cache
• Supports internal DMA engine

• Up to Four External Memory Interface (EMIF) module with ECC
• Supports LPDDR4 memory types
• Supports speeds up to 4266 MT/s
• Up to 4x32-b bus with inline ECC up to 68 GB/s

• General-Purpose Memory Controller (GPMC)
• 3x512KB on-chip SRAM in MAIN domain, protected by ECC Functional Safety:
• Functional Safety-Compliant targeted (on select part numbers)
• Developed for functional safety applications
• Documentation available to aid ISO 26262 functional safety system design up to ASIL-D/SIL-3 targeted
• Systematic capability up to ASIL-D/SIL-3 targeted
• Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
• Hardware integrity up to ASIL-B/SIL-2 targeted for Main Domain
• Hardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main Domain
• Safety-related certification
• ISO 26262 planned


• AEC-Q100 qualilfied on part number variants ending in Q1 Device security (on select part numbers):
• Secure boot with secure runtime support
• Customer programmable root key, up to RSA-4K or ECC-512
• Embedded hardware security module
• Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES High speed serial interfaces:
• Integrated ethernet switch supporting up to 8 (TDA4xH) or 4 (TDA4xP) external ports
• Two ports support 5Gb, 10Gb USXGMII or 5Gb XFI
• All ports support 1Gb, 2.5Gb SGMII
• All ports can support QSGMII. A maximum of 2 (TDA4xH) or 1 (TDA4xP) QSGMII can be enabled and uses all 8 or 4 internal lanes

• Up to 4x2-L/2x4L (TDA4xH) or 2x2L/1x4L (TDA4xP) PCI-Express (PCIe) Gen3 controllers
• Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation

• One USB 3.0 dual-role device (DRD) subsystem
• Enhanced SuperSpeed Gen1 Port
• Supports Type-C switching
• Independently configurable as USB host, USB peripheral, or USB DRD

• Three CSI2.0 4L RX plus Two CSI2.0 4L TX Ethernet
• Two RGMII/RMII interfaces Automotive interfaces:
• Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support Display subsystem:
• Two DSI 4L TX (up to 2.5k)
• One eDP/DP interface with Multi-Display Support (MST)
• One DPI Audio interfaces:
• Five Multichannel Audio Serial Port (MCASP) modules Video acceleration:
• H.264/H.265 Encode/Decode, up to 960MP/s (TDA4xH) or 480MP/s (TDA4xP) Flash memory interfaces:
• Embedded MultiMediaCard Interface ( eMMC™ 5.1)
• One Secure Digital 3.0 / Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0
• Universal Flash Storage (UFS 2.1) interface with two lanes
• Two independent flash interfaces configured as
• One OSPI or HyperBus™ or QSPI flash interfaces, and
• One QSPI flash interface
System-on-Chip (SoC) architecture:
• 16-nm FinFET technology
• 31 mm × 31 mm, 0.8-mm pitch, 1414-pin FCBGA (ALY), enables IPC class 3 PCB routing TPS6594-Q1 Companion Power Management ICs (PMIC):
• Functional Safety support up to ASIL-D
• Flexible mapping to support different use cases