TDA2PSX-ACD数据手册TI中文资料规格书

描述 Description

TI’s new TDA2Px System-on-Chip (SoC) is a highly optimized and scalable family ofdevices designed to meet the requirements of leading Advanced Driver Assistance Systems (ADAS). TheTDA2Px family enables broad ADAS applications in automobiles by integrating an optimal mix ofperformance, low power and ADAS vision analytics processing that aims to facilitate a moreautonomous and collision-free driving experience.
The TDA2Px SoC enables sophisticated embedded vision technology in automobiles bybroadest range of ADAS applications including front camera, park assist, surround view and sensorfusion on a single architecture.
The TDA2Px SoC incorporates a heterogeneous, scalable architecture that includes a mixof TI’s fixed and floating-point TMS320C66x digital signal processor (DSP) generation cores, VisionAccelerationPac, ARM Cortex-A15 MPCore™ and dual-Cortex-M4 processors. The integration of a videoaccelerator for decoding multiple video streams over an Ethernet AVB network, along with graphicsaccelerators for rendering virtual views, enable a 3D viewing experience. And the TDA2Px SoC alsointegrates a host of peripherals including multi-camera interfaces (both parallel and serial) forLVDS-based surround view systems, displays, CAN and GigB Ethernet AVB.
The Vision AccelerationPac for this family of products includes multiple embeddedvision engines (EVEs) offloading the vision analytics functionality from the application processorwhile also reducing the power footprint. The Vision AccelerationPac is optimized for visionprocessing with a 32-bit RISC core for efficient program execution and a vector coprocessor forspecialized vision processing.
Additionally, TI provides a complete set of development tools for the ARM, DSP, and EVEcoprocessor, including C compilers, a DSP assembly optimizer to simplify programming andscheduling, and a debugging interface for visibility into source code execution.
The TDA2Px ADAS processor is qualified according to the AEC-Q100 standard.
TI’s new TDA2Px System-on-Chip (SoC) is a highly optimized and scalable family of devicesdesigned to meet the requirements of leading Advanced Driver Assistance Systems (ADAS). The TDA2Pxfamily enables broad ADAS applications in automobiles by integrating an optimal mix of performance,low power and ADAS vision analytics processing that aims to facilitate a more autonomous andcollision-free driving experience.
The TDA2Px SoC enables sophisticated embedded vision technology in automobiles by broadest range of ADAS applications including front camera, park assist, surround view andsensor fusion on a single architecture.
The TDA2Px SoC incorporates a heterogeneous, scalable architecture that includes a mix ofTI’s fixed and floating-point TMS320C66x digital signal processor (DSP) generation cores, VisionAccelerationPac, ARM Cortex-A15 MPCore™ and dual-Cortex-M4 processors. The integration of a videoaccelerator for decoding multiple video streams over an Ethernet AVB network, along with graphicsaccelerators for rendering virtual views, enable a 3D viewing experience. And the TDA2Px SoC alsointegrates a host of peripherals including multi-camera interfaces (both parallel and serial) forLVDS-based surround view systems, displays, CAN and GigB Ethernet AVB.
The Vision AccelerationPac for this family of products includes multiple embedded visionengines (EVEs) offloading the vision analytics functionality from the application processor whilealso reducing the power footprint. The Vision AccelerationPac is optimized for vision processingwith a 32-bit RISC core for efficient program execution and a vector coprocessor for specializedvision processing.
Additionally, TI provides a complete set of development tools for the ARM, DSP, and EVEcoprocessor, including C compilers, a DSP assembly optimizer to simplify programming andscheduling, and a debugging interface for visibility into source code execution.
The TDA2Px ADAS processor is qualified according to the AEC-Q100 standard.

特性 Features

• Architecture Designed for ADAS Applications
• Video, Image, and Graphics Processing Support•Full-HD Video (1920 × 1080p, 60fps)
• Multiple Video Input and Video Output
• Dual ARM® Cortex®-A15 Microprocessor Subsystem
• Up to Two C66x™ Floating-Point VLIW DSP
• Fully Object-Code Compatible With C67x™ and C64x+™
• Up to Thirty-two 16 × 16-Bit Fixed-Point Multiplies per Cycle
• Up to 2.5MB of On-Chip L3 RAM
• Level 3 (L3) and Level 4 (L4) Interconnects
• Two DDR2/DDR3/DDR3L Memory Interface (EMIF) Modules
• Supports up to DDR2-800 and DDR3-1333
• Up to 2GB Supported per EMIF•Dual ARM® Cortex®-M4 Image Processing Units (IPU)
• Vision AccelerationPac
• Upto Two Embedded Vision Engines (EVEs)
• Imaging Subsystem (ISS)
• Image Signal Processor (ISP)
• Wide Dynamic Range andLens Distortion Correction (WDR and Mesh LDC)
• One CameraAdaptation Layer (CAL_B)
• IVA-HD Subsystem
• Display Subsystem
• Display Controller With DMAEngine and up to Three Pipelines
• HDMI™ Encoder: HDMI 1.4a and DVI 1.0Compliant
• 2D-Graphics Accelerator (BB2D) Subsystem
• Vivante™ GC320Core
• Video Processing Engine (VPE)
• Dual-Core PowerVR® SGX544 3D GPU
• Two Video Input Port (VIP) Modules
• Support for up to EightMultiplexed Input Ports
• General-Purpose Memory Controller (GPMC)
• Enhanced Direct Memory Access (EDMA) Controller
• 2-Port Gigabit Ethernet (GMAC)
• Up to two Controller Area Network (DCAN) Modules
• CAN 2.0BProtocol
• Modular Controller Area Network (MCAN) Module
• CAN 2.0B Protocol with available FD (Flexible Data Rate) functionality
• MIPI® CSI-2 Camera Serial Interface•PCI Express® 3.0 Port With Integrated PHY
• One 2-lane Gen2-Compliant Port
• or Two 1-laneGen2-Compliant Ports
• Sixteen 32-Bit General-Purpose Timers •32-Bit MPU Watchdog Timer
• Ten Configurable UART/IrDA/CIR Modules
• Four Multichannel Serial Peripheral Interfaces (McSPI)
• Quad SPI Interface
• Five Inter-Integrated Circuit (I2C) Ports
• SATA Interface
• Eight Multichannel Audio Serial Port (McASP) Modules
• SuperSpeed USB 3.0 Dual-Role Device
• Three High-Speed USB 2.0 Dual-Role Devices
• Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC/SD/SDIO)
• Up to 247 General-Purpose I/O (GPIO) Pins
• Device security features
• Hardware Crypto accelerators and DMA
• Firewalls
• JTAG lock
• Securekeys
• Secure ROM and boot
• Power, Reset, and Clock Management
• On-Chip Debug With CTools Technology
• Automotive AEC-Q100 Qualified
• 28-nm CMOS Technology •23 mm × 23 mm, 0.8-mm Pitch, 784-Pin BGA (ACD)All trademarks are the property of their respective owners.