首页 >TBSN74LV74ADR>规格书列表

零件编号	下载订购	功能描述/丝印	制造商上传企业	LOGO
74LV74	文件：125.21 Kbytes Page：12 Pages	DualD-typeflip-flopwithsetandreset;positive-edgetrigger DESCRIPTION The74LV74isalow-voltageSi-gateCMOSdeviceandispinandfunctioncompatiblewith74HC/HCT74. FEATURES •Wideoperatingvoltage:1.0to5.5V •OptimizedforLowVoltageapplications:1.0to3.6V •AcceptsTTLinputlevelsbetweenVCC=2.7VandVCC=3.6V •Ty	PhilipsPhilips Semiconductors 飞利浦荷兰皇家飞利浦	Philips
74LV74	文件：251.4 Kbytes Page：15 Pages	DualD-typeflip-flopwithsetandreset;positive-edgetrigger 1.Generaldescription The74LV74isadualpositiveedgetriggeredD-typeflip-flopwithindividualdata(nD),clock(nCP), set(nSD)andreset(nRD)inputs,andcomplementarynQandnQoutputs.DataattheD-inputthat meetstheset-upandholdtimerequirementsontheLOW-to-HIGHclocktrans	NEXPERIANexperia B.V. All rights reserved 安世安世半导体(中国)有限公司	NEXPERIA
74LV74A	文件：444.43 Kbytes Page：16 Pages	DUALPOSITIVE-EDGE-TRIGGEREDD-TYPEFLIP-FLOPS	TITexas Instruments 德州仪器美国德州仪器公司	TI
74LV74D	文件：251.4 Kbytes Page：15 Pages	DualD-typeflip-flopwithsetandreset;positive-edgetrigger 1.Generaldescription The74LV74isadualpositiveedgetriggeredD-typeflip-flopwithindividualdata(nD),clock(nCP), set(nSD)andreset(nRD)inputs,andcomplementarynQandnQoutputs.DataattheD-inputthat meetstheset-upandholdtimerequirementsontheLOW-to-HIGHclocktrans	NEXPERIANexperia B.V. All rights reserved 安世安世半导体(中国)有限公司	NEXPERIA
74LV74D	文件：125.21 Kbytes Page：12 Pages	DualD-typeflip-flopwithsetandreset;positive-edgetrigger DESCRIPTION The74LV74isalow-voltageSi-gateCMOSdeviceandispinandfunctioncompatiblewith74HC/HCT74. FEATURES •Wideoperatingvoltage:1.0to5.5V •OptimizedforLowVoltageapplications:1.0to3.6V •AcceptsTTLinputlevelsbetweenVCC=2.7VandVCC=3.6V •Ty	PhilipsPhilips Semiconductors 飞利浦荷兰皇家飞利浦	Philips
74LV74DB	文件：125.21 Kbytes Page：12 Pages	DualD-typeflip-flopwithsetandreset;positive-edgetrigger DESCRIPTION The74LV74isalow-voltageSi-gateCMOSdeviceandispinandfunctioncompatiblewith74HC/HCT74. FEATURES •Wideoperatingvoltage:1.0to5.5V •OptimizedforLowVoltageapplications:1.0to3.6V •AcceptsTTLinputlevelsbetweenVCC=2.7VandVCC=3.6V •Ty	PhilipsPhilips Semiconductors 飞利浦荷兰皇家飞利浦	Philips
74LV74N	文件：125.21 Kbytes Page：12 Pages	DualD-typeflip-flopwithsetandreset;positive-edgetrigger DESCRIPTION The74LV74isalow-voltageSi-gateCMOSdeviceandispinandfunctioncompatiblewith74HC/HCT74. FEATURES •Wideoperatingvoltage:1.0to5.5V •OptimizedforLowVoltageapplications:1.0to3.6V •AcceptsTTLinputlevelsbetweenVCC=2.7VandVCC=3.6V •Ty	PhilipsPhilips Semiconductors 飞利浦荷兰皇家飞利浦	Philips
74LV74PW	文件：251.4 Kbytes Page：15 Pages	DualD-typeflip-flopwithsetandreset;positive-edgetrigger 1.Generaldescription The74LV74isadualpositiveedgetriggeredD-typeflip-flopwithindividualdata(nD),clock(nCP), set(nSD)andreset(nRD)inputs,andcomplementarynQandnQoutputs.DataattheD-inputthat meetstheset-upandholdtimerequirementsontheLOW-to-HIGHclocktrans	NEXPERIANexperia B.V. All rights reserved 安世安世半导体(中国)有限公司	NEXPERIA
74LV74PW	文件：125.21 Kbytes Page：12 Pages	DualD-typeflip-flopwithsetandreset;positive-edgetrigger DESCRIPTION The74LV74isalow-voltageSi-gateCMOSdeviceandispinandfunctioncompatiblewith74HC/HCT74. FEATURES •Wideoperatingvoltage:1.0to5.5V •OptimizedforLowVoltageapplications:1.0to3.6V •AcceptsTTLinputlevelsbetweenVCC=2.7VandVCC=3.6V •Ty	PhilipsPhilips Semiconductors 飞利浦荷兰皇家飞利浦	Philips
74LV74PWDH	文件：125.21 Kbytes Page：12 Pages	DualD-typeflip-flopwithsetandreset;positive-edgetrigger DESCRIPTION The74LV74isalow-voltageSi-gateCMOSdeviceandispinandfunctioncompatiblewith74HC/HCT74. FEATURES •Wideoperatingvoltage:1.0to5.5V •OptimizedforLowVoltageapplications:1.0to3.6V •AcceptsTTLinputlevelsbetweenVCC=2.7VandVCC=3.6V •Ty	PhilipsPhilips Semiconductors 飞利浦荷兰皇家飞利浦	Philips

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