SY89875U中文资料Dividers数据手册Microchip规格书

描述 Description

This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency using a programmable divider to create a lower speed version of the input clock. Available divider ratios are 2, 4, 8 and 16, or straight pass-through.The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF-AC reference is included for AC-coupled applications.The /RESET input asynchronously resets the divider. In the pass-through function (divide by 1) the /RESET synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /IN).

特性 Features

• Integrated programmable clock divider and 1:2 fanout buffer
• Guaranteed AC performance over temperature and voltage:
• >2.0GHz fMAX
• <200ps tr/tf
• <15ps within device skew
• Low jitter design:
• <10psPP total jitter
• <1psRMS cycle-to-cycle jitter
• Unique input termination and VTPin for DC-coupled and AC-coupled Inputs; CML, PECL, LVDS and HSTL
• LVDS compatible outputs
• TTL/CMOS inputs for select and reset
• Parallel programming capability
• Programmable divider ratios of 1, 2, 4, 8 and 16
• Low voltage operation 2.5V
• Output disable function
• -40°C to 85°C temperature range
• Available in 16-pin (3mm x 3mm) MLF® package

简介

SY89875U属于集成电路（IC）的时钟缓冲器驱动器。由制造生产的SY89875U时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。