SY898531L中文资料Buffers数据手册Microchip规格书

描述 Description

The SY898531L is a 3.3V, low skew, 1:9 LVPECL fanout buffer with two selectable clock input pairs. Most standard differential input levels can be applied to the CLK, /CLK pair while LVPECL, CML, or SSTL input levels can be applied to the PCLK, /PCLK pair. To eliminate runt pulses on the outputs during asynchronous assertion/de-assertion of the clock enable pin, the clock enable is synchronized with the input signal.The SY898531L operates from a 3.3V ±5% supply and is guaranteed over the full industrial temperature range of 0°C to +70°C. The SY898531L is part of Micrel’s highspeed, Precision Edge product line.

特性 Features

• Provides nine differential 3.3V LVPECL copies
• Selects between differential CLK, /CLK or LVPECL clock inputs
• CLK, /CLK pair accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL input levels
• PCLK, /PCLK pair accepts LVPECL, CML, SSTL input levels
• Guaranteed AC performance over temperature and supply voltage:
• 500MHz Maximum output frequency
• <2ns Propagation delay (In-to-Q)
• <50ps Output skew
• <250ps Part-to-part skew
• Additive phase jitter, RMS: 0.17ps (typical)
• 3.3V ±5% supply voltage
• 0°C to +70°C temperature operating range
• Available in a 32-pin TQFP package

简介

SY898531L属于集成电路（IC）的时钟缓冲器驱动器。由制造生产的SY898531L时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。