SY89871U数据手册集成电路（IC）的时钟缓冲器驱动器规格书PDF

描述 Description

The SY89871U is a 2.5V/3.3VLVPECL output precision clock divider capable of accepting a high-speeddifferential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS clockinput signal and dividing down the frequency using a programmable divider ratioto create a frequency locked lower speed version of the input clock (BankB).Available divider ratios are 2, 4, 8 and 16. In a typical 622MHz clocksystem this would provide availability of 311MHz, 155MHz, 77MHz, or 38MHzauxiliary clock components.The differential input buffer has a unique internal termination designthat allows access to the termination network through a VT pin. Thisfeature allows the device to easily interface to different logic standards. AVREF-AC reference is included for AC-coupled applications.The SY89871Uincludes two phase-matched output banks. Bank A (QA) is a frequency-matchedcopy of the input. Bank B (QB0, QB1) is a divided down output of the inputfrequency. Bank A and Bank B maintain a matched delay independent of the dividersetting.

特性 Features

• Bank A: undivided pass-through (QA)
• Bank B: programmable divide by 2, 4, 8, 16 (QB0, QB1)
• Matched delay: all outputs have matched delay, independent of divider setting
• >2.5GHz fMAX
•

简介

SY89871U属于集成电路（IC）的时钟缓冲器驱动器。由制造生产的SY89871U时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。