SY55856U中文资料Skew Management数据手册Microchip规格书

描述 Description

The SY55856U is a 2.5GHz, two-channel, fully differential CML (Current Mode Logic) delay line. The device is optimized to adjust the relative delay between two channels, such as clock and data, in 50ps increments. Both inputs may be adjusted in either direction in 7 increments of 50ps, for a total adjustment range of ±350ps. In addition, the clock input maybe inverted through the CINV control pin.The SY55856U inputs are designed to accept singleended or differential CML signals. The differential CML outputs are optimized for 50Ω loads (50Ω source terminated), thus only requires a single 100Ω resistor across the output pair. Output rise and fall time is an extremely fast 110ps(max) and the differential swing is 400mV. The maximum throughput of the SY55856U is guaranteed to exceed 2.5GHz (5Gbps).

特性 Features

• Guaranteed AC parameters over temp and voltage
• >2.5GHz fMAX
• <384ps prop delay
• <120ps tr/tf
• Delay either clock or data
• 50ps increments
• ±350ps total delay
• Source terminated CML outputs
• Full differential I/O
• Wide supply voltage spectrum: 2.3V to 3.6V
• Available in a tiny 32-pin EPAD-TQFP package

简介

SY55856U属于集成电路（IC）的延迟线。由制造生产的SY55856U延迟线时钟延迟线产品族中的产品属于数字器件，用于在数字信号中引入时间延迟，以便将提交给器件输入的信号跃迁，经过某一已知时间之后在输出端复现。它们常用于高速数字系统，以校正或补偿不同信号路径之间的信号传播时间的偏差。这些器件可用于产生固定、可选或可变持续时间的延迟。