SY100E137中文资料8-Bit Ripple Counter数据手册Microchip规格书

描述 Description

The SY10/100E137 are very high speed binary ripple counters. The two least significant bits were designed with very fast edge rates, while the more significant bits maintain standard ECLinPS output edge rates. This allows the counters to operate at very high frequencies, while maintaining a moderate power dissipation level.The devices are ideally suited for multiple frequency clock generation, as well as for counters in highperformance ATE time measurement boards.Both asynchronous and synchronous enables are available to maximize the device's flexibility for various applications. The asynchronous enable input, A_Start, when asserted, enables the counter while overriding any synchronous enable signals. The E137 features XOR'ed enable inputs, EN1 and EN2, which are synchronous to the CLK input. When only one synchronous enable is asserted, the counter becomes disabled on the next CLK transition. All outputs remain in the previous state poised for the other synchronous enable or A_Start to be asserted in order to re-enable the counter. Asserting both synchronous enables causes the counter to become enabled on the next transition of the CLK. EN1 (or EN2) and CLK edges are coincident. Sufficient delay has been inserted in the CLK path (to compensate for the XOR gate delay and the internal D-flip-flop set-up time) to ensure that the synchronous enable signal is clocked correctly; hence, the counter is disabled.The E137 can also be driven single-endedly utilizing the VBB output supply as the voltage reference for the CLK input signal. If a single-ended signal is to be used, the VBB pin should be connected to the CLK input and bypassed to ground via a 0.01μF capacitor. VBB can only source/sink 0.5mA; therefore, it should be used as a switching reference for the E137 only.All input pins left open will be pulled LOW via an input pull-down resistor. Therefore, do not leave the differential CLK inputs open. Doing so causes the current source transistor of the input clock gate to become saturated, thus upsetting the internal bias regulators and jeopardizing the stability of the device.The asynchronous Master Reset resets the counter to an all zero state upon assertion.

特性 Features

1.8GHz min. count frequency
Extended 100E VEE range of -4.2V to -5.5V
Synchronous and asynchronous enable pins
Differential clock input and data output pins
VBB output for single-ended use
Asynchronous Master Reset
Internal 75KO input pull-down resistors
Available in 28-pin PLCC packge

简介

SY100E137属于集成电路（IC）的计数器除法器。由制造生产的SY100E137计数器，除法器计数器和除法器 IC 是数字逻辑器件，可对输入发生的逻辑转换进行计数，然后使用多个并行输出重新发送累加的计数，和/或生成单个输出信号转换，从而对应用某些整数数量输入信号转换进行响应。除了简单的事件计数，它们还可用于各种频率合成应用。