N-channel 650 V, 0.095 廓, 24 A, MDmesh??V Power MOSFET in D짼PAK, I짼PAK, TO-220FP, TO-220, TO-247

Description These devices are N-channel MDmesh™ V Power MOSFETs based on an innovative proprietary vertical process technology, which is combined with STMicroelectronics’ well-known PowerMESH™ horizontal layout structure. The resulting product has extremely low on-resistance, which is unmatched a

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STMICROELECTRONICS

意法半导体

丝印：D2PAK；Package：TO-263；isc N-Channel MOSFET Transistor

文件：314.08 Kbytes 页数：2 Pages

ISC

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N沟道650 V、0.095 Ohm、24 A MDmesh M5功率MOSFET，D2PAK封装

This device is an N-channel Power MOSFET based on the MDmesh™ M5 innovative vertical process technology combined with the well-known PowerMESH™ horizontal layout. The resulting product offers extremely low on-resistance, making it particularly suitable for applications requiring high power and super • Extremely low RDS(on) \n• Low gate charge and input capacitance \n• Excellent switching performance \n• 100% avalanche tested;

ST

意法半导体

isc N-Channel MOSFET Transistor

DESCRIPTION • Low Drain-Source On-Resistance FEATURES • Drain Current –ID=24A@ TC=25℃ • Drain Source Voltage- : VDSS= 650V(Min) • Static Drain-Source On-Resistance : RDS(on) = 119mΩ (Max) • 100 avalanche tested • Minimum Lot-to-Lot variations for robust device performance and re

文件：310.87 Kbytes 页数：2 Pages

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N-channel 650 V, 0.095 廓, 24 A, MDmesh??V Power MOSFET in D짼PAK, I짼PAK, TO-220FP, TO-220, TO-247

Description These devices are N-channel MDmesh™ V Power MOSFETs based on an innovative proprietary vertical process technology, which is combined with STMicroelectronics’ well-known PowerMESH™ horizontal layout structure. The resulting product has extremely low on-resistance, which is unmatched a

文件：1.27883 Mbytes 页数：22 Pages

STMICROELECTRONICS

意法半导体

isc N-Channel MOSFET Transistor

DESCRIPTION • Low Drain-Source On-Resistance FEATURES • Drain Current –ID=22A@ TC=25℃ • Drain Source Voltage- : VDSS= 650V(Min) • Static Drain-Source On-Resistance : RDS(on) = 148mΩ (Max) • 100 avalanche tested • Minimum Lot-to-Lot variations for robust device performance and re

文件：358.39 Kbytes 页数：2 Pages

ISC

无锡固电