SSTUM32868ET数据手册恩XP中文资料规格书

描述 Description

Overview Archived content is no longer updated and is made available for historical reference only.
The SSTUM32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank by four (2R x 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally required two registers in a single package, thereby freeing up board real-estate and facilitating routing to accommodate high-density Dual In-line Memory Module (DIMM) designs.
The SSTUM32868 also integrates a parity function, which accepts a parity bit from the memory controller, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active LOW).
It further offers added features over the JEDEC standard register in that it is permanently configured for high output drive strength. This allows use in high density designs with heavier than normal net loading conditions. Furthermore, the SSTUM32868 features two additional chip select inputs, which allow more versatile enabling and disabling in densely populated memory modules. Both added features (drive strength and chip selects) are fully backward compatible to the JEDEC standard register. Finally, the SSTUM32868 is optimized for the fastest propagation delay in the SSTU family of registers.
The SSTUM32868 is packaged in a 176-ball, 8 x 22 grid, 0.65 mm ball pitch, thin profile fine-pitch ball grid array (TFBGA) package, which (while requiring a minimum 6 mm x 15 mm of board space) allows for adequate signal routing and escape using conventional card technology.

特性 Features

•28-bit data register supporting DDR2

•Fully compliant to JEDEC standard for SSTUB32868

•Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two JEDEC-standard DDR2 registers (that is, 2 x SSTUA32864 or 2 x SSTUA32866)

•Parity checking function across 22 input data bits

•Parity out signal

•Controlled multi-impedance output impedance drivers enable optimal signal integrity and speed

•Meets or exceeds SSTUB32868 JEDEC standard speed performance

•Supports up to 450 MHz clock frequency of operation

•Permanently configured for high output drive

•Optimized pinout for high-density DDR2 module design

•Chip-selects minimize power consumption by gating data outputs from changing state

•Two additional chip select inputs allow optional flexible enabling and disabling

•Supports Stub Series Terminated Logic SSTL_18 data inputs

•Differential clock (CK and CK) inputs

•Supports Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) switching levels on the control and RESET inputs

•Single 1.8 V supply operation (1.7 V to 2.0 V)

•Available in 176-ball 6 mm x 15 mm, 0.65 mm ball pitch TFBGA package

应用 Application

400 MT/s to 800 MT/s high-density (for example, 2 rank by 4) DDR2 registered DIMMs

DDR2 Registered DIMMs (RDIMM) desiring parity checking functionality