SSTUH32865ET数据手册恩XP中文资料规格书

描述 Description

Overview Archived content is no longer updated and is made available for historical reference only.
The SSTUH32865 is a 1.8 V 28-bit high output drive 1:2 register specifically designed for use on two rank by four (2R x 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally required two registers in a single package, thereby freeing up board real-estate and facilitating routing to accommodate high-density Dual In-line Memory Module (DIMM) designs.
The SSTUH32865 also integrates a parity function, which accepts a parity bit from the memory controller, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active LOW).
The SSTUH32865 is packaged in a 160-ball, 12 x 18 grid, 0.65 mm ball pitch, thin profile fine-pitch ball grid array (TFBGA) package, which-while requiring a minimum 9 mm x 13 mm of board space-allows for adequate signal routing and escape using conventional card technology.
The SSTUH32865 is identical to SSTU32865 in function and performance, with higher-drive outputs optimized to drive heavy load nets (such as stacked DRAMs) while maintaining speed and signal integrity.

特性 Features

•28-bit data register supporting DDR2

•Higher output drive strength version of SSTU32865 optimized for high-capacitive load nets

•Fully compliant to JEDEC standard JESD82-9

•Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two JEDEC-standard DDR2 registers (that is, 2 x SSTU32864 or 2 x SSTU32866)

•Parity checking function across 22 input data bits

•Parity out signal

•Controlled output impedance drivers enable optimal signal integrity and speed

•Exceeds JESD82-9 speed performance (1.8 ns max. single-bit switching propagation delay, 2.0 ns max. mass-switching)

•Supports up to 450 MHz clock frequency of operation

•Optimized pinout for high-density DDR2 module design

•Chip-selects minimize power consumption by gating data outputs from changing state

•Supports Stub Series Terminated Logic SSTL_18 data inputs

•Differential clock (CK and CK) inputs

•Supports Low Voltage Complementary Metal Oxide Silicon (LVCMOS) switching levels on the control and RESET inputs

•Single 1.8 V supply operation

•Available in 160-ball 9 mm x 13 mm, 0.65 mm ball pitch TFBGA package

应用 Application

High-density (for example, 2 rank by 4) DDR2 registered DIMMs

DDR2 Registered DIMMs (RDIMM) desiring parity checking functionality

Stacked or planar high-DRAM count registered DIMMs