SSTE

SURFACE MOUNT SUPER FAST RECTIFIERS

PRV:50-1000Volts Io:2.5Amperes FEATURES: *Highcurrentcapability *Highsurgecurrentcapability *Highreliability *Lowreversecurrent *Lowforwardvoltagedrop *Superfastrecoverytime *Pb/RoHSFree

SSTE

SURFACE MOUNT SUPER FAST RECTIFIERS

PRV:50-1000Volts Io:2.5Amperes FEATURES: *Highcurrentcapability *Highsurgecurrentcapability *Highreliability *Lowreversecurrent *Lowforwardvoltagedrop *Superfastrecoverytime *Pb/RoHSFree

SSTE32882KB1

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT

Features •PinoutoptimizesDDR3RDIMMPCBlayout •DDR3-800/1066/1333/1600/1866/2133rate •1-to-2RegisterOutputsand1-to-4ClockPairOutputssupportstackedDDR3RDIMMs •PhaseLockLoopclockdriverforbufferingonedifferentialclockpair(CKandCK)anddistributingtofourdifferent

SSTE32882KB1

LOW POWER DDR3 Register + PLL; • DDR3-800/1066/1333/1600/1866/2133 rate\n• 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs support stacked DDR3 RDIMMs\n• Phase Lock Loop clock driver for buffering one differential clock pair (CK and CK) and distributing to four differential outputs\n• Supports LVCMOS switching levels on the RESET and MIRROR inputs\n• Checks priority on DIMM-independent data inputs\n• Supports dynamic 1T/3T timing transaction and output inversion feature for improved timing performance during normal operations and MRS command pass-through\n• Supports CKE Power Down operation modes\n• Supports Quad Chip Select operation features\n• RESET input disables differential input recievers, resets all registers, and disables all output drivers except ERROUT and QnCKEn\n• Provides access to internal control words for configuring the device features and adapting in different RDIMM and system applications\n• Latch-up performance exceeds 100mA\n• ESD > 2000V per MIL-STD883, Method 3015; ESD > 200V using machine model (c = 200pF, R = 0)\n;

This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.25V, 1.35V and 1.5V VDD operation

SSTEAKG8

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT

Features •PinoutoptimizesDDR3RDIMMPCBlayout •DDR3-800/1066/1333/1600/1866/2133rate •1-to-2RegisterOutputsand1-to-4ClockPairOutputssupportstackedDDR3RDIMMs •PhaseLockLoopclockdriverforbufferingonedifferentialclockpair(CKandCK)anddistributingtofourdifferent

SSTE32882HLB

Pinout optimizes DDR3 RDIMM PCB layout

SSTE32882KA1

Pinout optimizes DDR3 RDIMM PCB layout

SSTE32882KB1

Pinout optimizes DDR3 RDIMM PCB layout

SSTE32882HLBAKG8

Package：176-TFBGA；包装：卷带（TR） 类别：集成电路（IC） 应用特定时钟/定时 描述：IC REGISTERING CLK DRIVER 176BGA

Renesas Electronics America Inc

SSTE32882KA1AKG

Package：176-TFBGA；包装：卷带（TR） 类别：集成电路（IC） 应用特定时钟/定时 描述：IC REGISTERING CLK DRIVER 176BGA

Renesas Electronics America Inc