DDR3 Register + PLL

This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.25V, 1.35V and 1.5V VDD operation • DDR3-800/1066/1333/1600/1866/2133 rate\n• Phase Lock Loop clock driver for buffering one differential clock pair (CK and CK) and distributing to four differential outputs\n• Checks priority on DIMM-independent data inputs\n• Supports CKE Power Down operation modes\n• RESET input disables different;

Renesas

瑞萨

Pinout optimizes DDR3 RDIMM PCB layout

文件：1.68385 Mbytes 页数：75 Pages

IDT

Package：176-TFBGA；包装：卷带（TR） 类别：集成电路（IC） 应用特定时钟/定时 描述：IC REGISTERING CLK DRIVER 176BGA

Renesas Electronics America Inc

Package：176-TFBGA；包装：卷带（TR） 类别：集成电路（IC） 应用特定时钟/定时 描述：IC REGISTERING CLK DRIVER 176BGA

Renesas Electronics America Inc