SN74LVTH543数据手册集成电路（IC）的缓冲器驱动器接收器收发器规格书PDF

描述 Description

These octal transceivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
The ’LVTH543 devices contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (LEAB\\ or LEBA\\) and output-enable (OEAB\\ or OEBA\\) inputs are provided for each register, to permit independent control in either direction of data flow.
The A-to-B enable (CEAB)\\ input must be low to enter data from A or to output data from B. If CEAB\\ is low and LEAB\\ is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB\\ puts the A latches in the storage mode. With CEAB\\ and OEAB\\ both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar, but requires using the CEBA\\, LEBA\\, and OEBA\\ inputs.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

特性 Features

• Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
• Typical VOLP (Output Ground Bounce)    CC = 3.3 V, TA = 25°C
• Support Unregulated Battery Operation Down to 2.7 V
• Ioff and Power-Up 3-State Support Hot Insertion
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Latch-Up Performance Exceeds 500 mA Per JESD 17
• ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
• 200-V Machine Model (A115-A)