SN74LVTH273-EP中文资料具有清零端的增强型产品 3.3V Abt 八路 D 型触发器数据手册TI规格书

描述 Description

This octal D-type flip-flop is designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. The SN74LVTH273 is a positive-edge-triggered flip-flop with a direct-clear (CLR)\\ input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

特性 Features

• Controlled Baseline
• Enhanced Diminishing Manufacturing Sources (DMS) Support
• Qualification Pedigree
• Typical VOLP (Output Ground Bounce)    CC = 3.3 V, TA = 25°C
• Buffered Clock and Direct-Clear Inputs
• Ioff Supports Partial Power-Down-Mode Operation
• Latch-Up Performance Exceeds 500 mA Per JESD 17
• 2000-V Human-Body Model (A114-A)
• 200-V Machine Model (A115-A)

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.