SN74LV32A-Q1数据手册TI中文资料规格书

描述 Description

These quadruple 2-input positive-OR gates are designed for 2-V to 5.5-V VCC operation. The SN74LV32A performs the Boolean function Y = A + B or Y = A • B in positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

特性 Features

• Qualified for Automotive Applications
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• 2-V to 5.5-V VCC Operation
• Max tpd of 6.5 ns at 5 V
• Typical VOLP (Output Ground Bounce)    CC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)    >2.3 V at VCC = 3.3 V, TA = 25°C
• Supports Mixed-Mode Voltage Operation on All Ports
• Ioff Supports Partial-Power-Down Mode Operation