SN74LV244AT数据手册集成电路（IC）的缓冲器驱动器接收器收发器规格书PDF

描述 Description

This octal buffer/driver is designed specifically to improve both the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters. The SN74LV244AT is organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE shall be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

特性 Features

• Inputs Are TTL-Voltage Compatible
• 4.5-V to 5.5-V VCC Operation
• Typical tpd = 5.4 ns at 5 V
• Typical VOLP (Output Ground Bounce) CC = 5 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 5 V, TA = 25°C
• Supports Mixed-Mode Voltage Operation on All Ports
• Ioff Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• ESD Protection Exceeds JESD 22
• 2000-V Human-Body Model (A114-A)
• 200-V Machine Model (A115-A)
• 1000-V Charged-Device Model (C101)