SN74LV240A数据手册集成电路（IC）的缓冲器驱动器接收器收发器规格书PDF

描述 Description

These octal buffers/drivers with inverted outputs are designed for 2-V to 5.5-V VCC operation.

The ’LV240A devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

These devices are organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

特性 Features

• 2-V to 5.5-V VCC Operation
• Max tpd of 6.5 ns at 5 V
• Typical VOLP (Output Ground Bounce) VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C
• Support Mixed-Mode Voltage Operation on All Ports
• Latch-Up Performance Exceeds 250 mA per JESD 17
• Ioff Supports Live Insertion, Partial Power-Down Mode, and Back Drive Protection
• ESD Protection Exceeds JESD 22
• 2000-V Human-Body Model (A114-A)
• 200-V Machine Model (A115-A)
• 1000-V Charged-Device Model (C101)