19-BIT BUS INTERFACE

4.5-V to 5.5-V VCC Operation 1.4-kΩ Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors Designed for IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications Flow-Through Architecture Optimizes PCB Layout Latc

文件：496.34 Kbytes 页数：18 Pages

TI

德州仪器

19-BIT BUS INTERFACE

文件：186.9 Kbytes 页数：7 Pages

TI

德州仪器

19-BIT BUS INTERFACE

文件：329.37 Kbytes 页数：13 Pages

TI

德州仪器

19 位总线接口

The SN74LV161284 is designed for 4.5-V to 5.5-V VCC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.\nThis device has eight bidirectional bits; data can flow in the A-to-B direction when • 4.5-V to 5.5-V VCC Operation\n• Designed for IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications\n• Latch-Up Performance Exceeds 250 mA Per JEDEC 17\n• 300-V Machine Model (A115-A)\n• 2000-V Charged-Device Model (C101);

TI

德州仪器

丝印：LV161284；Package：TSSOP；19-BIT BUS INTERFACE

4.5-V to 5.5-V VCC Operation 1.4-kΩ Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors Designed for IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications Flow-Through Architecture Optimizes PCB Layout Latc

文件：496.34 Kbytes 页数：18 Pages

TI

德州仪器

丝印：LV161284；Package：TSSOP；19-BIT BUS INTERFACE

4.5-V to 5.5-V VCC Operation 1.4-kΩ Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors Designed for IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications Flow-Through Architecture Optimizes PCB Layout Latc

文件：496.34 Kbytes 页数：18 Pages

TI

德州仪器

丝印：LV161284；Package：SSOP；19-BIT BUS INTERFACE

4.5-V to 5.5-V VCC Operation 1.4-kΩ Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors Designed for IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications Flow-Through Architecture Optimizes PCB Layout Latc

文件：496.34 Kbytes 页数：18 Pages

TI

德州仪器

丝印：LV161284；Package：SSOP；19-BIT BUS INTERFACE

4.5-V to 5.5-V VCC Operation 1.4-kΩ Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors Designed for IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications Flow-Through Architecture Optimizes PCB Layout Latc

文件：496.34 Kbytes 页数：18 Pages

TI

德州仪器

丝印：LV161284；Package：SSOP；19-BIT BUS INTERFACE

4.5-V to 5.5-V VCC Operation 1.4-kΩ Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors Designed for IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications Flow-Through Architecture Optimizes PCB Layout Latc

文件：496.34 Kbytes 页数：18 Pages

TI

德州仪器

丝印：LV161284；Package：SSOP；19-BIT BUS INTERFACE

4.5-V to 5.5-V VCC Operation 1.4-kΩ Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors Designed for IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications Flow-Through Architecture Optimizes PCB Layout Latc

文件：496.34 Kbytes 页数：18 Pages

TI

德州仪器