丝印：LV161284；Package：TSSOP；19-BIT BUS INTERFACE

4.5-V to 5.5-V VCC Operation 1.4-kΩ Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors Designed for IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications Flow-Through Architecture Optimizes PCB Layout Latc

文件：496.34 Kbytes 页数：18 Pages

TI

德州仪器

丝印：LV161284；Package：TSSOP；19-BIT BUS INTERFACE

4.5-V to 5.5-V VCC Operation 1.4-kΩ Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors Designed for IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications Flow-Through Architecture Optimizes PCB Layout Latc

文件：496.34 Kbytes 页数：18 Pages

TI

德州仪器

丝印：LV161284；Package：SSOP；19-BIT BUS INTERFACE

4.5-V to 5.5-V VCC Operation 1.4-kΩ Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors Designed for IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications Flow-Through Architecture Optimizes PCB Layout Latc

文件：496.34 Kbytes 页数：18 Pages

TI

德州仪器

丝印：LV161284；Package：SSOP；19-BIT BUS INTERFACE

4.5-V to 5.5-V VCC Operation 1.4-kΩ Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors Designed for IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications Flow-Through Architecture Optimizes PCB Layout Latc

文件：496.34 Kbytes 页数：18 Pages

TI

德州仪器

丝印：LV161284；Package：SSOP；19-BIT BUS INTERFACE

4.5-V to 5.5-V VCC Operation 1.4-kΩ Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors Designed for IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications Flow-Through Architecture Optimizes PCB Layout Latc

文件：496.34 Kbytes 页数：18 Pages

TI

德州仪器

丝印：LV161284；Package：SSOP；19-BIT BUS INTERFACE

4.5-V to 5.5-V VCC Operation 1.4-kΩ Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors Designed for IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications Flow-Through Architecture Optimizes PCB Layout Latc

文件：496.34 Kbytes 页数：18 Pages

TI

德州仪器