SN74LS74

DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP

DUALD-TYPEPOSITIVEEDGE-TRIGGEREDFLIP-FLOP TheSN54/74LS74Adualedge-triggeredflip-floputilizesSchottkyTTLcircuitrytoproducehighspeedD-typeflip-flops.Eachflip-flophasindividualclearandsetinputs,andalsocomplementaryQandQoutputs. InformationatinputDistransferred

SN74LS74

LOW POWER SCHOTTKY

TheSN74LS74Adualedge-triggeredflip-floputilizesSchottkyTTLcircuitrytoproducehighspeedD-typeflip-flops.Eachflip-flophasindividualclearandsetinputs,andalsocomplementaryQandQoutputs. InformationatinputDistransferredtotheQoutputonthepositive-goingedgeof

SN74LS74

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

SN74LS74

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLIP-FLOPS WITH PRESET AND CLEAR

SN74LS74

LOW POWER SCHOTTKY;

SN74LS748D

10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS

10-LINE-TO-4-LINEAND8-LINE-TO-3-LINEPRIORITYENCODERS TheSN54/74LS147andtheSN54/74LS148arePriorityEncoders.Theyprovideprioritydecodingoftheinputstoensurethatonlythehighestorderdatalineisencoded.Bothdeviceshavedatainputsandoutputswhichareactiveatthelowlo

SN74LS748N

10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS

10-LINE-TO-4-LINEAND8-LINE-TO-3-LINEPRIORITYENCODERS TheSN54/74LS147andtheSN54/74LS148arePriorityEncoders.Theyprovideprioritydecodingoftheinputstoensurethatonlythehighestorderdatalineisencoded.Bothdeviceshavedatainputsandoutputswhichareactiveatthelowlo

SN74LS74A

LOW POWER SCHOTTKY

TheSN74LS74Adualedge-triggeredflip-floputilizesSchottkyTTLcircuitrytoproducehighspeedD-typeflip-flops.Eachflip-flophasindividualclearandsetinputs,andalsocomplementaryQandQoutputs. InformationatinputDistransferredtotheQoutputonthepositive-goingedgeof

SN74LS74A

DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY;

DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOPThe SN54/74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary Q and Q outputs.\nInformation at input D is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or the LOW level, the D input signal has no effect.

恩XP

SN74LS74A

具有预置和清零端的双路正边沿触发式 D 型触发器; • Package Options Include Plastic “Small Outline\" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs\n• Dependable Texas Instruments Quality and Reliability;

These devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the D input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs. The SN54' family is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74' family is characterized for operation from 0°C to 70°C.