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74LS73

DUALJKNEGATIVEEDGE-TRIGGEREDFLIP-FLOP

DUALJKNEGATIVEEDGE-TRIGGEREDFLIP-FLOP TheSN54LS/74LS73AoffersindividualJ,K,clear,andclockinputs.Thesedualflip-flopsaredesignedsothatwhentheclockgoesHIGH,theinputsareenabledanddatawillbeaccepted.ThelogicleveloftheJandKinputsmaybeallowedtochangewhenthe

MotorolaMotorola, Inc

摩托罗拉加尔文制造公司

74LS73

DualNegative-Edge-TriggeredMaster-SlaveJ-KFlip-FlopswithClearandComplementaryOutputs

GeneralDescription Thisdevicecontainstwoindependentnegative-edge-triggeredJ-Kflip-flopswithcomplementaryoutputs.TheJandKdataisprocessedbytheflip-flopsonthefallingedgeoftheclockpulse.Theclocktriggeringoccursatavoltagelevelandisnotdirectlyrelatedtothetra

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

74LS73

DualJ-KFlip-Flops(withClear)

DualJ-KFlip-Flops(withClear)

HitachiHitachi Semiconductor

日立日立公司

74LS73

DUALJ-KFLIP-FLOPSWITHCLEAR

TITexas Instruments

德州仪器美国德州仪器公司

74LS73A

DUALJ-KFLIP-FLOPSWITHCLEAR

TITexas Instruments

德州仪器美国德州仪器公司

74LS73A

DualNegative-Edge-TriggeredMaster-SlaveJ-KFlip-FlopswithClearandComplementaryOutputs

GeneralDescription Thisdevicecontainstwoindependentnegative-edge-triggeredJ-Kflip-flopswithcomplementaryoutputs.TheJandKdataisprocessedbytheflip-flopsonthefallingedgeoftheclockpulse.Theclocktriggeringoccursatavoltagelevelandisnotdirectlyrelatedtothetra

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

74LS73A

DualJ-KFlip-Flops(withClear)

DualJ-KFlip-Flops(withClear)

HitachiHitachi Semiconductor

日立日立公司

74LS73N

DualJKFllp-FlopProductSpecification

DESCRIPTION The'73isadualflip-flopwithindividual J,K,ClockanddirectResetinputs.The 7473ispositivepulse-triggered.JKinfor- mationisloadedintothemasterwhile theClockisHIGHandtransferredtothe slaveontheHIGH-to-LOWtransition. Forthe7473,theJandKinputs

ETC1List of Unclassifed Manufacturers

etc未分类制造商未分类制造商

DM74LS73A

DualNegative-Edge-TriggeredMaster-SlaveJ-KFlip-FlopswithClearandComplementaryOutputs

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

DM74LS73A

DualNegative-Edge-TriggeredMaster-SlaveJ-KFlip-FlopswithClearandComplementaryOutputs

GeneralDescription Thisdevicecontainstwoindependentnegative-edge-triggeredJ-Kflip-flopswithcomplementaryoutputs.TheJandKdataisprocessedbytheflip-flopsonthefallingedgeoftheclockpulse.Theclocktriggeringoccursatavoltagelevelandisnotdirectlyrelatedtothetra

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

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