丝印：SN74F377AN；Package：PDIP；OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE

Contains Eight D-Type Flip-Flops With Single-Rail Outputs Clock Enable Latched to Avoid False Clocking Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators Buffered Common Enable Input Package Options Include Plastic Small-Outline Packages and Standard Plast

文件：588.41 Kbytes 页数：13 Pages

TI

德州仪器

Octal D-Type Flip-Flop with Clock Enable

General Description The 74F377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one set

文件：62.13 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

Octal D-Type Flip-Flop with Clock Enable

文件：75.98 Kbytes 页数：7 Pages

FAIRCHILD

仙童半导体

Octal D-type flip-flop with enable

DESCRIPTION The 74F377A has 8 edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low. The register is fully edge triggered. The state of each D input, one set-up time befor

文件：84.15 Kbytes 页数：10 Pages

PHI

PHI