74F377A技术资料参数原装现货飞利浦PHILIPS-114ic电子网

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型号	下载订购	功能描述	制造商上传企业	LOGO
74F377A	文件：84.15 Kbytes Page：10 Pages	Octal D-type flip-flop with enable DESCRIPTION The 74F377A has 8 edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low. The register is fully edge triggered. The state of each D input, one set-up time befor 文件：84.15 Kbytes 页数：10 Pages	PHI PHI	PHI
74F377A	文件：300 bytes Page：1 Pages	Octal D-type flip-flop with enable	恩XP	恩XP
74F377AD	文件：300 bytes Page：1 Pages	74系列逻辑芯片	恩XP	恩XP
74F377PC	文件：143.07 Kbytes Page：8 Pages	Octal D Flip-Flop with Clock Enable 文件：143.07 Kbytes 页数：8 Pages	NSC 国半	NSC
74F377SC	文件：143.07 Kbytes Page：8 Pages	Octal D Flip-Flop with Clock Enable 文件：143.07 Kbytes 页数：8 Pages	NSC 国半	NSC
N74F377AD	文件：84.15 Kbytes Page：10 Pages	Octal D-type flip-flop with enable DESCRIPTION The 74F377A has 8 edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low. The register is fully edge triggered. The state of each D input, one set-up time befor 文件：84.15 Kbytes 页数：10 Pages	PHI PHI	PHI

更多74F377A供应商更新时间2026-10-23 16:00:00