74系列逻辑芯片

恩XP

Octal D Flip-Flop with Clock Enable

文件：143.07 Kbytes 页数：8 Pages

NSC

国半

Octal D Flip-Flop with Clock Enable

文件：143.07 Kbytes 页数：8 Pages

NSC

国半

Octal D-type flip-flop with enable

DESCRIPTION The 74F377A has 8 edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low. The register is fully edge triggered. The state of each D input, one set-up time befor

文件：84.15 Kbytes 页数：10 Pages

PHI

PHI