SN74CBTD3384C中文资料具有 –2V 下冲保护的 5V、1:1 (SPST)、10 通道通用 FET 总线开关数据手册TI规格书

描述 Description

The SN74CBTD3384C is a high-speed TTL-compatible FET bus switch with low ON-state resistance, allowing for minimal propagation delay. This device features an integrated diode to VCC to provide level shifting for 5-V input down to 3.3-V output levels. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBTD3384C provides protection for undershoot down to –2 V by sensing an undershoot event and ensuring that the switch remains in the proper state.

The SN74CBTD3384C is organized as two 5-bit bus switches with separate output-enable (OE)\\ inputs. It can be used as two 5-bit bus switches or as one 10-bit bus switch. When OE\\ is low, the associated 5-bit bus switch is ON, and port A is connected to port B. When OE\\ is high, the associated 5-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE\\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CBTD3384C is a high-speed TTL-compatible FET bus switch with low ON-state resistance, allowing for minimal propagation delay. This device features an integrated diode to VCC to provide level shifting for 5-V input down to 3.3-V output levels. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBTD3384C provides protection for undershoot down to –2 V by sensing an undershoot event and ensuring that the switch remains in the proper state.

The SN74CBTD3384C is organized as two 5-bit bus switches with separate output-enable (OE)\\ inputs. It can be used as two 5-bit bus switches or as one 10-bit bus switch. When OE\\ is low, the associated 5-bit bus switch is ON, and port A is connected to port B. When OE\\ is high, the associated 5-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE\\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

特性 Features

• Undershoot Protection for Off-Isolation on A and B Ports Up To –2 V
• Bidirectional Data Flow, With Near-Zero Propagation Delay
• Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 5 pF Typical)
• VCC Operating Range From 4.5 V to 5.5 V
• Control Inputs Can be Driven by TTL or 5-V/3.3-V CMOS Outputs
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• 2000-V Human-Body Model (A114-B, Class II)
• Supports Both Digital and Analog Applications: Memory Interleaving, Bus Isolation, Low-Distortion Signal Gating