SN74AUP1T04数据手册集成电路（IC）的门反相器规格书PDF

特性 Features

• Single-Supply Voltage Translator
• Output Level Up to Supply VCC CMOS Level
- 1.8 V to 3.3 V (at VCC = 3.3 V)
• 2.5 V to 3.3 V (at VCC = 3.3 V)
• 1.8 V to 2.5 V (at VCC = 2.5 V)
• 3.3 V to 2.5 V (at VCC = 2.5 V
• Schmitt-Trigger Inputs Reject Input Noise and Provide Better Output Signal Integrity
• Ioff Supports Partial Power Down (VCC = 0 V)
• Very Low Static Power Consumption: 0.1 µA
• Very Low Dynamic Power Consumption: 0.9 µA
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• Pb-Free Packages Available: SC-70 (DCK) 2 × 2.1 × 0.65 mm (Height 1.1 mm)
• More Gate Options Available at www.ti.com/littlelogic
• ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model (A114-B, Class II)
• 1000-V Charged-Device Model (C101)