SN74AUP1G126中文资料具有三态输出的单路 0.8V 至 3.6V 低功耗缓冲器数据手册TI规格书

描述 Description

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family assures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see AUP – The Lowest-Power Family and Excellent Signal Integrity ).

This bus buffer gate is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is low. This device has the input-disable feature, which allows floating input signals.

To assure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

特性 Features

• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• 2000-V Human-Body Model (A114-B, Class II)
• Available in the Texas Instruments NanoStar™ Package
• Low Dynamic-Power Consumption (Cpd = 4 pF Typical at 3.3 V)
• Low Noise – Overshoot and Undershoot CC
• Ioff Supports Partial-Power-Down Mode Operation
• Wide Operating VCC Range of 0.8 V to 3.6 V
• 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
• Suitable for Point-to-Point Applications