SN74AUP1G34中文资料单路 0.8V 至 3.6V 低功耗缓冲器数据手册TI规格书

描述 Description

This single buffer gate performs the Boolean function Y = A in positive logic.

特性 Features

• Available in the Ultra Small 0.64 mm2 Package (DPW) with 0.5-mm Pitch
• Low Dynamic-Power Consumption; Cpd = 4.1 pF Typ at 3.3 V
• Low Noise - Overshoot and Undershoot CC
• Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typ at 3.3 V)
• Optimized for 3.3-V Operation
• tpd = 4.1 ns Max at 3.3 V
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• 2000-V Human-Body Model (A114-B, Class II)
• 1000-V Charged-Device Model (C101)