SN74ALVTH162244数据手册集成电路（IC）的缓冲器驱动器接收器收发器规格书PDF

描述 Description

The 'ALVTH162244 devices are 16-bit buffers/line drivers designed for low-voltage 2.5-V or 3.3-V VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.These devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide true outputs and symmetrical active-low output-enable (OE\\) inputs. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. When VCC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE\\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. All outputs are designed to sink up to 12 mA and include equivalent 30-resistors to reduce overshoot and undershoot. The SN54ALVTH162244 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALVTH162244 is characterized for operation from -40°C to 85°C.

特性 Features

• State-of-the-Art Advanced BiCMOS Technology (ABT) WidebusTM Design for 2.5-V and 3.3-V Operation and Low Static Power Dissipation
• Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC)
• Typical VOLP (Output Ground Bounce) CC = 3.3 V, TA = 25°C
• Power Off Disables Outputs, Permitting Live Insertion
• High-Impedance State During Power Up and Power Down Prevents Driver Conflict
• Uses Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating
• Output Ports Have Equivalent 30- Series Resistors, So No External Resistors Are Required
• Auto3-State Eliminates Bus Current Loading When Output Exceeds VCC + 0.5 V
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model; and Exceeds 1000 V Using Charged-Device Model, Robotic Method
• Flow-Through Architecture Facilitates Printed Circuit Board Layout
• Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
• Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package
NOTE: For order entry: The DGG package is abbreviated to G, and the DGV package is abbreviated to V. Widebus is a trademark of Texas Instruments Incorporated.