SN74ALVCH32973中文资料具有 8 个独立缓冲器的 16 位总线收发器和透明 D 类锁存器数据手册TI规格书

描述 Description

This device contains eight independent noninverting buffers and a 16-bit noninverting bus transceiver and D-type latch, designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH32973 is particularly suitable for demultiplexing an address/data bus into a dedicated address bus and dedicated data bus. The device is used where there is asynchronous bidirectional communication between the A and B data bus, and the address signals are latched and buffered on the Q bus. The control-function implementation minimizes external timing requirements.
This device can be used as one 8-bit buffer, two 8-bit transceivers, and two 8-bit latches or one 8-bit buffer, one 16-bit transceiver, and one 16-bit latch. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The transceiver output-enable (TOE)\\ input can be used to disable the transceivers so that the A and B buses effectively are isolated.
When the latch-enable (LE) input is high, the Q outputs follow the data (A) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the A inputs. The latch output-enable (LOE)\\ input can be used to place the nine Q outputs in either a normal logic state (high or low logic level) or the high-impedance state. In the high-impedance state, the Q outputs neither drive nor load the bus lines significantly. LOE\\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the Q outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, LOE\\ and TOE\\ should be tied to VCC through pullup resistors; the minimum values of the resistors are determined by the current-sinking capability of the drivers.
The eight independent noninverting buffers perform the Boolean function Y = D, and are independent of the state of DIR, TOE\\, LE, and LOE\\.
The A and B I/Os, and D inputs have bus-hold circuitry. Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

特性 Features

• Member of the Texas Instruments Widebus+™ Family
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• 200-V Machine Model (A115-A)
• 1000-V Charged-Device Model (C101)
Widebus+ is a trademark of Texas Instruments.