DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

文件：138.06 Kbytes 页数：9 Pages

TI

德州仪器

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

文件：1.04581 Mbytes 页数：19 Pages

TI

德州仪器

Package：16-SOIC（0.209"，5.30mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：设置（预设）和复位 类别：集成电路（IC） 触发器 描述：IC FF JK TYPE DUAL 1BIT 16SO

TI

德州仪器

Dual J-K positive edge-triggered flip-flop with set and reset

DESCRIPTION The 74ALS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active-Low inputs and operate independently of the clock (CP) input. The J and K ar

文件：93.6 Kbytes 页数：9 Pages

PHI

PHI

Dual J-K positive edge-triggered flip-flop with set and reset

DESCRIPTION The 74ALS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active-Low inputs and operate independently of the clock (CP) input. The J and K ar

文件：93.6 Kbytes 页数：9 Pages

PHI

PHI

Dual J-K positive edge-triggered flip-flop with set and reset

DESCRIPTION The 74ALS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active-Low inputs and operate independently of the clock (CP) input. The J and K ar

文件：93.6 Kbytes 页数：9 Pages

PHI

PHI