9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：368.8 Kbytes 页数：17 Pages

TI

德州仪器

9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

文件：590.98 Kbytes 页数：16 Pages

TI

德州仪器

9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

文件：120.46 Kbytes 页数：17 Pages

TI

德州仪器

具有三态输出的 9 位总线接口 D 类锁存器

The 'ABT843 9-bit latches are designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The nine transparent D-type latches provide true data at • State-of-the-ArtEPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17• Typical VOLP (Output Ground Bounce) CC = 5 V, TA = 25°C• High-Drive Outputs (-32-mA IOH, 64-mA IOL)• Package Options Include Plastic Small-Outline (DW);

TI

德州仪器

丝印：AB843；Package：SSOP；9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：368.8 Kbytes 页数：17 Pages

TI

德州仪器

丝印：AB843；Package：SSOP；9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：368.8 Kbytes 页数：17 Pages

TI

德州仪器

丝印：ABT843；Package：SOIC；9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：368.8 Kbytes 页数：17 Pages

TI

德州仪器

丝印：ABT843；Package：SOIC；9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：368.8 Kbytes 页数：17 Pages

TI

德州仪器

丝印：ABT843；Package：SOIC；9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：368.8 Kbytes 页数：17 Pages

TI

德州仪器

丝印：ABT843；Package：SOIC；9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：368.8 Kbytes 页数：17 Pages

TI

德州仪器